bcm8128 ? multirate 10-gbps sonet/sdh/10ge/fec mux bcm8128 functional block diagram ? 10-gigabit msa (multi-source agreement) compliant ? fully integrated clock multiplication unit (cmu) supports multiple rates: oc-192, 10ge, 10gfc and its fec rates ? 16:1 multiplexer with lvds data input ? configurable divide by 16 or 32 clock modes ? configurable lvds input clock-to-data bus timing skew control ? on-chip 16 x 10 fifo eliminates system timing issues ? serial data polarity invert ? bit order reversal ? low jitter 10 gigabit output clock for retiming lased tx clock output ? lock detect ? core power supply: 1.8v ? i/o power supply: cml at 1.8v, lvds and cmos at 1.8v or 3.3v ? power consumption: 450 mw ? standard cmos fabrication process ? 127-pin bga package available in standard and pb-free version ? compliant with optical internetworking forum (oif), telcordia, itu-t, ansi, and ieee 802.3ae industry standards. ? reduces design cycle and time to market. ? high level of integration allows for higher port density solutions. ? uses the most effective silicon economy of scale for cmos- based devices. ? low-power consumption eliminates the need for external cooling sources. features summary of benefits ? oc-192/stm-64/10ge transmission equipment ? sonet/sdh optical modules ? add/drop multiplexers ? digital cross-connects ? atm switch backbones ? sonet test equipment ? terabit routers ? edge routers applications 10-gb serial data xsbi (16 bit) parallel data xsbi (16 bit) parallel data bcm8129 orx orx orx orx bcm8128 bcm8129 bcm8128 network interface processor network interface processor
overview ? phone: 949-450-8700 fax: 949-450-8710 e-mail: info@broadcom.com web: www.broadcom.com broadcom corporation 16215 alton parkway, p.o. box 57013 irvine, california 92619-7013 ? 2006 by broadcom corporation. all rights reserved. 8128-pb03-r 02/02/06 broadcom ? , the pulse logo, connecting everything ? , and the connecting everything logo are among the trademarks of broadcom corporation and/or its aff iliates in the united states, certain other countries and/or the eu. any other trademarks or trade name s mentioned are the property of their respective owners. the bcm8128 is a fully integrated msa-compliant quad-rate sonet/ sdh/10ge transmitter operating at oc-192 (9.953 gbps), 10ge (10.3125 gbps), 10gfc (10.513 gbps), and forward error correction (fec) data rates (10.664/10.709, 11.096, or 11.31 gbps) with serializer and clock multiplication unit (cmu). the low-jitter lvds interface and onboard low-jitter pll exceed optical internetworking forum (oif), ieee 802.3ae, telcordia, ansi, and itu-t jitter standards. the bcm8128 reference clock input frequency is user-selectable to the line rate divided by either 16 or 64. the two reference clock outputs can be squelched under user control. the bcm8128 provides skew control between the lvds transmit parallel input clock and data to accommodate difficult timing variances. a 10-word fifo decouples the parallel input timing domain from the serial output timing domain. the bcm8128 provides a cml serial output clock to retime the data at the optical interface. the bcm8128 can be powered with a single 1.8v supply or dual 1.8/ 3.3v supply without any special power supply sequencing requirements. the bcm8128 comes in a 11 x 11 mm, 127-pin bga package. txreset rb_skew txpiclksel txskewsel0/1 txpiclkp txpiclkn polsel lsbsel txdin0p txdin0n txdin15p txdin15n txratesel0 txratesel1 txrefclkp txrefsel vcpclnpll txrefclkn pdclnpll sysclkp sysclkn fifo control skew control write pointer read pointer 16 x 10 fifo input register 16:1 mux output retime divide-by-16 divide-by-4 10ghz cmu phase detector charge pump txfifoerr tsdp tsdn tsclkp tsclkn txpclkp txpclkn txlockerr txmclkp txmclkn cml 10g serial data outpu t cml 10g clock output divide by 16 clock output selectable divide by 16 or 64 clock output divide by 16 or 32 lvds clock divide by 16 or 64 lvpecl reference clock
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